The present invention relates to a complementary metal oxide semiconductor (CMOS) Pierce crystal oscillator, and in particular, to a clock generator with activation control.
FIG. 1a shows a conventional crystal pad 100a, for generating a clock signal. To generate the clock signal, input pad 101 and output pad 103 are coupled to an oscillation source, such as a crystal circuit, such that an oscillating signal can be amplified by amplifier 102 and output to shaping circuit 104. The oscillating signal is typically a sinusoidal wave, and the shaping circuit 104 can be a shaping buffer for shaping the oscillating signal to a desired square wave, thereby the circuit 100a functions as a clock generator. Such architecture is very popular, reliable, easy to design and economical, but suffers from some disadvantages such as uncertain start time. As shown in FIG. 1b, conventionally, a counter logic 107 is provided to solve the problem. The counter logic 107 is capable of accumulating square wave transitions, and asserting a ready signal when the total number of transitions meets a predetermined value. The counter design, however, incurs additional cost, and additionally, suffers from problems such as false counting due to glitches, thereby causing systems to crash.
FIG. 1c shows another crystal pad 100b according to the related art. The input pad 101, amplifier 102 and output pad 103 are analogous to FIG. 1a. The shaping circuit 104, however, is substituted by a hysteresis circuit 105, but maintains popularity and reliability, easy of design and low cost. Although when using small hysteresis devices, false counting still prevails if the counter logic 107 exists (as shown in FIG. 1d), and when using large hysteresis devices, unbalanced duty cycles may easily occur due to power bouncing. Large hysteresis devices may also have too large a threshold to push. Therefore, an optimum design for hysteresis circuit 105 is difficult. In FIG. 1d, the counter logic 107 comprises a built-in power on reset (POR) for resetting the counter at power on. The logic, however, is limited to detecting whether the clock generator is ready for use.